HD64F2357F20V Datasheet, PDF(133/1049 Page) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

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HD64F2357F20V Datasheet, PDF (133/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

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Section 6 Bus Controller

6.1 Overview

The H8S/2357 Group has a on-chip bus controller (BSC) that manages the external address space divided into eight areas.

The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling

multiple memories to be connected easily.

The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU,

DMA controller (DMAC), and data transfer controller (DTC).

6.1.1 Features

The features of the bus controller are listed below.

â¢ Manages external address space in area units

ï£§ In advanced mode, manages the external space as 8 areas of 2-Mbytes

ï£§ Bus specifications can be set independently for each area

ï£§ DRAM/burst ROM interfaces can be set

â¢ Basic bus interface

ï£§ Chip select (CS0 to CS7) can be output for areas 0 to 7

ï£§ 8-bit access or 16-bit access can be selected for each area

ï£§ 2-state access or 3-state access can be selected for each area

ï£§ Program wait states can be inserted for each area

â¢ DRAM interface

ï£§ DRAM interface can be set for areas 2 to 5 (in advanced mode)

ï£§ Row address/column address multiplexed output (8/9/10 bits)

ï£§ Two byte access methods (2-CAS)

ï£§ Burst operation (fast page mode)

ï£§ TP cycle insertion to secure RAS precharging time

ï£§ Choice of CAS-before-RAS refreshing or self-refreshing

â¢ Burst ROM interface

ï£§ Burst ROM interface can be set for area 0

ï£§ Choice of 1- or 2-state burst access

â¢ Idle cycle insertion

ï£§ An idle cycle can be inserted in case of an external read cycle between different areas

ï£§ An idle cycle can be inserted in case of an external write cycle immediately after an external read cycle

â¢ Write buffer functions

ï£§ External write cycle and internal access can be executed in parallel

ï£§ DMAC single-address mode and internal access can be executed in parallel

â¢ Bus arbitration function

ï£§ Includes a bus arbiter that arbitrates bus mastership among the CPU, DMAC, and DTC

Rev.6.00 Oct.28.2004 page 103 of 1016

REJ09B0138-0600H

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