HD64F2357F20V Datasheet, PDF (274/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

8.2 Register Descriptions
8.2.1 DTC Mode Register A (MRA)
Bit
:
Initial value :
R/W
:
7
SM1
Unde-
fined
—
6
SM0
Unde-
fined
—
5
DM1
Unde-
fined
—
4
DM0
Unde-
fined
—
3
MD1
Unde-
fined
—
2
MD0
Unde-
fined
—
1
DTS
Unde-
fined
—
0
Sz
Unde-
fined
—
MRA is an 8-bit register that controls the DTC operating mode.
Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is to be incremented,
decremented, or left fixed after a data transfer.
Bit 7
SM1
0
1
Bit 6
SM0
—
0
1
Description
SAR is fixed
SAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
SAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
Bits 5 and 4—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether DAR is to be incremented,
decremented, or left fixed after a data transfer.
Bit 5
DM1
0
1
Bit 4
DM0
—
0
1
Description
DAR is fixed
DAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
DAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode.
Bit 3
MD1
0
1
Bit 2
MD0
0
1
0
1
Description
Normal mode
Repeat mode
Block transfer mode
—
Rev.6.00 Oct.28.2004 page 244 of 1016
REJ09B0138-0600H