HD64F2357F20V Datasheet, PDF(276/1049 Page) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

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HD64F2357F20V Datasheet, PDF (276/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

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8.2.3

Bit

DTC Source Address Register (SAR)

: 23 22 21 20 19

Initial value : Unde- Unde- Unde- Unde- Unde-

fined fined fined fined fined

R/W

:â â ââ â

âââ

âââ

âââ

âââ

4 3 2 10

Unde- Unde- Unde- Unde- Unde-

fined fined fined fined fined

â â â ââ

SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer,

specify an even source address.

8.2.4 DTC Destination Address Register (DAR)

Bit

: 23 22 21 20 19

Initial value : Unde- Unde- Unde- Unde- Unde-

fined fined fined fined fined

R/W

:â â ââ â

âââ

âââ

âââ

âââ

4 3 2 10

Unde- Unde- Unde- Unde- Unde-

fined fined fined fined fined

â â â ââ

DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size

transfer, specify an even destination address.

8.2.5

Bit

DTC Transfer Count Register A (CRA)

: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Initial value : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde-

fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined

R/W

:â â ââ â â ââ â â ââ â â ââ

âï£§ï£§ï£§ï£§ï£§ï£§ï£§ CRAH ï£§ï£§ï£§ï£§ï£§ï£§â âï£§ï£§ï£§ï£§ï£§ï£§ï£§ CRAL ï£§ï£§ï£§ï£§ï£§ï£§â

CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.

In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is decremented by 1 every time

data is transferred, and transfer ends when the count reaches H'0000.

In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits

(CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is

decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00. This

operation is repeated.

8.2.6

Bit

DTC Transfer Count Register B (CRB)

: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Initial value : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde-

fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined

R/W

:â â ââ â â ââ â â ââ â â ââ

Rev.6.00 Oct.28.2004 page 246 of 1016

REJ09B0138-0600H

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