HD64F2357F20V Datasheet, PDF (388/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

Bit 3 Bit 2 Bit 1 Bit 0
Channel IOA3 IOA2 IOA1 IOA0 Description
1
0 0 0 0 TGR1A is Output disabled
(Initial value)
1
output _{Initial output is 0 0 output at compare match}
1
0
compare _output
register
1 output at compare match
1
Toggle output at compare
match
100
Output disabled
1
10
Initial output is 1 0 output at compare match
output
1 output at compare match
1
Toggle output at compare
match
1 0 0 0 TGR1A is Capture input Input capture at rising edge
1
input
source is
capture TIOCA1 pin
1
×
register
Input capture at falling edge
Input capture at both edges
1
×
×
Capture input Input capture at generation of
source is TGR0A channel 0/TGR0A compare
compare match/ match/input capture
input capture
×: Don’t care
Bit 3 Bit 2 Bit 1 Bit 0
Channel IOA3 IOA2 IOA1 IOA0 Description
2
0
0
0
0
TGR2A is Output disabled
(Initial value)
1
output _{Initial output is 0 0 output at compare match}
1
0
compare _output
register
1 output at compare match
1
Toggle output at compare
match
100
Output disabled
1
10
Initial output is 1 0 output at compare match
output
1 output at compare match
1
Toggle output at compare
match
1
×
0
0
TGR2A is Capture input Input capture at rising edge
1
input
source is
capture TIOCA2 pin
1
×
register
Input capture at falling edge
Input capture at both edges
×: Don’t care
Rev.6.00 Oct.28.2004 page 358 of 1016
REJ09B0138-0600H