HD64F2357F20V Datasheet, PDF (792/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

Item
Write data delay time
Symbol
t _WDD
Condition B
Min Max
—
30
Write data setup time t _WDS
Write data hold time t _WDH
WR setup time
t _WCS
WR hold time
t _WCH
CAS setup time
t _CSR
WAIT setup time
WAIT hold time
BREQ setup time
BACK delay time
Bus-floating time
BREQO delay time
t _WTS
t _WTH
t _BRQS
t _BACD
t _BZD
t _BRQOD
0.5 × —
t _cyc – 20
0.5 × —
t _cyc – 10
0.5 × —
t _cyc – 10
0.5 × —
t _cyc – 10
0.5 × —
t _cyc – 10
30
—
5
—
30
—
—
15
—
50
—
30
Condition C
Min Max
—
60
0.5 × —
t _cyc – 36
0.5 × —
t _cyc – 20
0.5 × —
t _cyc – 20
0.5 × —
t _cyc – 20
0.5 × —
t _cyc – 20
60
—
10
—
60
—
—
30
—
100
—
60
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions
Figure 22-72 to
Figure 22-79
Figure 22-76
Figure 22-74
Figure 22-80
Figure 22-81
(4) DMAC Timing
Table 22-39 lists the DMAC timing.
Table 22-39 DMAC Timing
Condition B: V_CC = 5.0 V ± 10%, AV_CC = 5.0 V ± 10%, V_ref = 4.5 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 2 to 20 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Condition C: V_CC = 3.0 V to 5.5 V, AV_CC = 3.0 V to 5.5 V, V_ref = 3.0 V to AV_CC, V_SS = AV_SS = 0V, ø = 2 to 13 MHz, T_a
= –20 to +75°C (regular specifications), T_a = –40 to +85°C (wide-range specifications)
Item
DREQ setup time
DREQ hold time
TEND delay time
DACK delay time 1
DACK delay time 2
Condition B Condition C
Symbol Min Max Min Max Unit
t _DRQS
30 — 40 — ns
t _DRQH
10 — 10 —
t _TED
— 20 — 40
t _DACD1
—
20
—
40
ns
t _DACD2
—
20
—
40
Test Conditions
Figure 22-85
Figure 22-84
Figure 22-82
Figure 22-83
Rev.6.00 Oct.28.2004 page 762 of 1016
REJ09B0138-0600H