HD64F2357F20V Datasheet, PDF (108/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

4.5 Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can
be executed at all times in the program execution state.
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as
specified in the instruction code.
Table 4-5 shows the status of CCR and EXR after execution of trap instruction exception handling.
Table 4-5 Status of CCR and EXR after Trap Instruction Exception Handling
Interrupt Control Mode
I
0
1
2
1
Legend:
1: Set to 1
0: Cleared to 0
—: Retains value prior to execution.
CCR
UI
—
—
I2 to I0
—
—
EXR
T
—
0
4.6 Stack Status after Exception Handling
Figure 4-4 shows the stack after completion of trap instruction exception handling and interrupt exception handling.
SP
CCR
PC
(24 bits)
SP
EXR
Reserved*
CCR
PC
(24 bits)
(a) Interrupt control mode 0
Note: * Ignored on return.
(b) Interrupt control mode 2
Figure 4-4 Stack Status after Exception Handling (Advanced Modes)
Rev.6.00 Oct.28.2004 page 78 of 1016
REJ09B0138-0600H