HD64F2357F20V Datasheet, PDF (363/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

Port G Data Direction Register (PGDDR)
Bit
:
7
6
5
4
3
2
1
0
—
—
— PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR
Modes 6, 7
Initial value : Undefined Undefined Undefined
0
0
0
0
0
R/W
:—
—
—
W
W
W
W
W
Modes 4, 5
Initial value : Undefined Undefined Undefined
1
0
0
0
0
R/W
:—
—
—
W
W
W
W
W
PGDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port G. PGDDR
cannot be read, and bits 7 to 5 are reserved. If PGDDR is read, an undefined value will be read.
The PG4DDR bit is initialized by a power-on reset and in hardware standby mode, to 1 in modes 4 and 5, and to 0 in
modes 6 and 7. It retains its prior state after a manual reset* and in software standby mode. The OPE bit in SBYCR is
used to select whether the bus control output pins retain their output state or become high-impedance when a transition is
made to software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
• Mode 7*
Setting a PGDDR bit to 1 makes the corresponding port G pin an output port, while clearing the bit to 0 makes the pin
an input port.
• Modes 4 to 6*
Pins PG₄ to PG₁ function as bus control output pins (CS0 to CS3) when the corresponding PGDDR bits are set to 1,
and as input ports when the bits are cleared to 0.
Pin PG₀ functions as the CAS output pin when DRAM interface is designated. Otherwise, setting the corresponding
PGDDR bit to 1 makes the pin an output port, while clearing the bit to 0 makes the pin an input port. For details of the
DRAM interfaces, see section 6, Bus Controller.
Note: * Modes 6 and 7 are provided in the on-chip ROM version only.
Port G Data Register (PGDR)
Bit
:
7
6
5
4
—
—
— PG4DR
Initial value : Undefined Undefined Undefined
0
R/W
:—
—
—
R/W
3
PG3DR
0
R/W
2
PG2DR
0
R/W
1
PG1DR
0
R/W
0
PG0DR
0
R/W
PGDR is an 8-bit readable/writable register that stores output data for the port G pins (PG₄ to PG₀).
Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified.
PGDR is initialized to H'00 (bits 4 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a
manual reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Rev.6.00 Oct.28.2004 page 333 of 1016
REJ09B0138-0600H