HD64F2357F20V Datasheet, PDF (629/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

19.10.2 Software Protection
Software protection can be implemented by setting the SWE bit in FLMCR1, erase block registers 1 and 2 (EBR1, EBR2),
and the RAMS bit in RAMER. When software protection is in effect, setting the P or E bit in flash memory control
register 1 (FLMCR1) does not cause a transition to program mode or erase mode. (See table 19-17.)
Table 19-17 Software Protection
Item
Description
SWE bit protection
• Clearing the SWE bit to 0 in FLMCR1 sets
the program/erase-protected state for all
blocks.
(Execute in on-chip RAM or external
memory.)
Block specification
protection
• Erase protection can be set for individual
blocks by settings in erase block registers
1 and 2 (EBR1, EBR2).
• Setting EBR1 and EBR2 to H'00 places all
blocks in the erase-protected state.
Emulation protection •
Setting the RAMS bit to 1 in the RAM
emulation register (RAMER) places all
blocks in the program/erase-protected
state.
Functions
Program Erase
Yes
Yes
—
Yes
Yes
Yes
19.10.3 Error Protection
In error protection, an error is detected when MCU runaway occurs during flash memory programming/erasing, or
operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted.
Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing.
If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error
protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase
mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting
the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode.
FLER bit setting conditions are as follows:
• When flash memory is read during programming/erasing (including a vector read or instruction fetch)
• Immediately after exception handling (excluding a reset) during programming/erasing
• When a SLEEP instruction (including software standby) is executed during programming/erasing
• When the CPU loses the bus during programming/erasing
Error protection is released only by a reset and in hardware standby mode.
Figure 19-21 shows the flash memory state transition diagram.
Rev.6.00 Oct.28.2004 page 599 of 1016
REJ09B0138-0600H