HD64F2357F20V Datasheet, PDF (841/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

Table A-5 Number of Cycles in Instruction Execution
Instruction Mnemonic
ADD
ADD.B #xx:8,Rd
ADD.B Rs,Rd
ADD.W #xx:16,Rd
ADD.W Rs,Rd
ADD.L #xx:32,ERd
ADD.L ERs,ERd
ADDS
ADDS #1/2/4,ERd
ADDX
ADDX #xx:8,Rd
ADDX Rs,Rd
AND
AND.B #xx:8,Rd
AND.B Rs,Rd
AND.W #xx:16,Rd
AND.W Rs,Rd
AND.L #xx:32,ERd
AND.L ERs,ERd
ANDC
ANDC #xx:8,CCR
ANDC #xx:8,EXR
BAND
BAND #xx:3,Rd
BAND #xx:3,@ERd
BAND #xx:3,@aa:8
BAND #xx:3,@aa:16
BAND #xx:3,@aa:32
Bcc
BRA d:8 (BT d:8)
BRN d:8 (BF d:8)
BHI d:8
BLS d:8
BCC d:8 (BHS d:8)
BCS d:8 (BLO d:8)
BNE d:8
BEQ d:8
BVC d:8
BVS d:8
BPL d:8
BMI d:8
BGE d:8
BLT d:8
BGT d:8
BLE d:8
BRA d:16 (BT d:16)
BRN d:16 (BF d:16)
BHI d:16
Branch
Byte Word
Instruction Address Stack
Data Data Internal
Fetch
Read
Operation Access Access Operation
I
J
K
L
M
N
1
1
2
1
3
1
1
1
1
1
1
2
1
3
2
1
2
1
2
1
2
1
3
1
4
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
1
2
1
Rev.6.00 Oct.28.2004 page 811 of 1016
REJ09B0138-0600H