HD64F2357F20V Datasheet, PDF (659/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

19.16.2 Flash Memory Control Register 2 (FLMCR2)
Bit
:
7
6
5
4
3
2
1
0
FLER
—
—
—
—
—
—
—
Initial value :
0
0
0
0
0
0
0
0
R/W
:
R
—
—
—
—
—
—
—
FLMCR2 is an 8-bit register that controls the flash memory operating modes. FLMCR2 is initialized to H'00 by a reset,
and in hardware standby mode and software standby mode.
When on-chip flash memory is disabled, a read will return H'00 and writes are invalid.
Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory
(programming or erasing). When FLER is set to 1, flash memory goes to the error-protection state.
Bit 7
FLER
0
1
Description
Flash memory is operating normally
Flash memory program/erase protection (error protection) is disabled
[Clearing condition]
Reset or hardware standby mode
An error has occurred during flash memory programming/erasing
Flash memory program/erase protection (error protection) is enabled
[Setting condition]
See section 19.19.3, Error Protection
(Initial value)
Bits 6 to 0—Reserved: These bits cannot be modified and are always read as 0.
19.16.3 Erase Block Register 1 (EBR1)
Bit
:
7
6
5
4
3
2
1
0
EBR1
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
Initial value :
0
0
0
0
0
0
0
0
R/W
: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a reset,
in hardware standby mode and software standby mode, and the SWE bit in FLMCR1 is not set. When a bit in EBR1 is set,
the corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR1 and EBR2 together
(setting more than one bit will automatically clear all EBR1 and EBR2 bits to 0). When on-chip flash memory is disabled,
a read will return H'00 and writes are invalid.
The flash memory block configuration is shown in table 19-33.
Rev.6.00 Oct.28.2004 page 629 of 1016
REJ09B0138-0600H