HD64F2357F20V Datasheet, PDF (226/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

7.5.2 Sequential Mode
Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode, MAR is updated after each
byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR.
One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in
DMACR.
Table 7-6 summarizes register functions in sequential mode.
Table 7-6 Register Functions in Sequential Mode
Register
23
MAR
23
15
H'FF
IOAR
15
ETCR
Legend:
MAR: Memory address register
IOAR: I/O address register
ETCR: Transfer count register
DTDIR:Data transfer direction bit
Function
DTDIR = 0 DTDIR = 1 Initial Setting
Operation
0 Source
address
register
Destination Start address of Incremented/
address transfer destination decremented every
register or transfer source transfer
0 Destination Source
address address
register register
Start address of Fixed
transfer source or
transfer destination
0 Transfer counter
Number of transfers Decremented every
transfer; transfer
ends when count
reaches H'0000
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or
decremented by 1 or 2 each time a byte or word is transferred.
IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF.
Rev.6.00 Oct.28.2004 page 196 of 1016
REJ09B0138-0600H