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HD64F2357F20V Datasheet, PDF (793/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series | |||
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(5) Timing of On-Chip Supporting Modules
Table 22-40 lists the timing of on-chip supporting modules.
Table 22-40 Timing of On-Chip Supporting Modules
Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC,
VSS = AVSS = 0 V, ø = 2 to 20 MHz, Ta = â20 to +75°C (regular specifications),
Ta = â40 to +85°C (wide-range specifications)
Condition C: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, Vref = 3.0 V to AVCC,
VSS = AVSS = 0 V, ø = 2 to 13 MHz, Ta = â20 to +75°C (regular specifications),
Ta = â40 to +85°C (wide-range specifications)
Item
PORT
PPG
TPU
TMR
SCI
Condition B
Symbol Min Max
Output data delay time t PWD
Input data setup time t PRS
Input data hold time
t PRH
Pulse output delay time t POD
Timer output delay time t TOCD
Timer input setup time t TICS
Timer clock input setup t TCKS
time
â 50
30 â
30 â
â 50
â 50
30 â
30 â
Timer clock Single t TCKWH 1.5 â
pulse width edge
Both
t TCKWL
2.5
â
edges
Timer output delay time tTMOD
Timer reset input setup tTMRS
time
â 50
30 â
Timer clock input setup tTMCS
time
30 â
Timer clock Single tTMCWH 1.5 â
pulse width edge
Both
t TMCWL
2.5 â
edges
Input clock Asynchro- t Scyc
4
â
cycle
nous
Synchro-
nous
6
â
Input clock pulse width
Input clock rise time
Input clock fall time
t SCKW
t SCKr
t SCKf
0.4 0.6
â 1.5
â 1.5
Condition C
Min Max Unit
â 75
ns
50 â
50 â
â 75
ns
â 75
ns
50 â
50 â
ns
1.5 â
t cyc
2.5 â
â 75
ns
50 â
ns
50 â
ns
1.5 â
t cyc
2.5 â
4
â
t cyc
6
â
0.4 0.6
t Scyc
â
1.5
t cyc
â 1.5
Test
Conditions
Figure 22-86
Figure 22-87
Figure 22-88
Figure 22-89
Figure 22-90
Figure 22-92
Figure 22-91
Figure 22-94
Rev.6.00 Oct.28.2004 page 763 of 1016
REJ09B0138-0600H
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