HD64F2357F20V Datasheet, PDF (136/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

6.1.3 Pin Configuration
Table 6-1 summarizes the pins of the bus controller.
Table 6-1 Bus Controller Pins
Name
Address strobe
Read
High write/write enable
Symbol I/O
AS
Output
RD
Output
HWR Output
Low write
LWR Output
Chip select 0
Chip select 1
Chip select 2/row address
strobe 2
CS0
Output
CS1
Output
CS2
Output
Chip select 3/row address
strobe 3
CS3
Output
Chip select 4/row address
strobe 4
CS4
Output
Chip select 5/row address
strobe 5
CS5
Output
Chip select 6
Chip select 7
Upper column address strobe
CS6
CS7
CAS
Output
Output
Output
Lower column strobe
Wait
LCAS
WAIT
Output
Input
Bus request
BREQ Input
Bus request acknowledge
BACK Output
Bus request output
BREQO Output
Function
Strobe signal indicating that address output on
address bus is enabled.
Strobe signal indicating that external space is
being read.
Strobe signal indicating that external space is to
be written, and upper half (D₁₅ to D₈) of data bus is
enabled.
2-CAS DRAM write enable signal.
Strobe signal indicating that external space is to
be written, and lower half (D₇ to D₀) of data bus is
enabled.
Strobe signal indicating that area 0 is selected.
Strobe signal indicating that area 1 is selected.
Strobe signal indicating that area 2 is selected.
DRAM row address strobe signal when area 2 is
in DRAM space.
Strobe signal indicating that area 3 is selected.
DRAM row address strobe signal when area 3 is
in DRAM space.
Strobe signal indicating that area 4 is selected.
DRAM row address strobe signal when area 4 is
in DRAM space.
Strobe signal indicating that area 5 is selected.
DRAM row address strobe signal when area 5 is
in DRAM space.
Strobe signal indicating that area 6 is selected.
Strobe signal indicating that area 7 is selected.
2-CAS DRAM upper column address strobe
signal.
DRAM lower column address strobe signal.
Wait request signal when accessing external 3-
state access space.
Request signal that releases bus to external
device.
Acknowledge signal indicating that bus has been
released.
External bus request signal used when internal
bus master accesses external space when
external bus is released.
Rev.6.00 Oct.28.2004 page 106 of 1016
REJ09B0138-0600H