HD64F2357F20V Datasheet, PDF (493/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

13.5 Usage Notes
13.5.1 Contention between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the T₂ state of a TCNT write cycle, the write takes priority and the timer
counter is not incremented. Figure 13-8 shows this operation.
TCNT write cycle
T₁
T₂
ø
Address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 13-8 Contention between TCNT Write and Increment
13.5.2 Changing Value of CKS2 to CKS0
If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation.
Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS2 to CKS0.
13.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is operating, errors could
occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the
mode.
13.5.4 System Reset by WDTOVF Signal
If the WDTOVF output signal* is input to the RES pin of the H8S/2357 Group, the H8S/2357 Group will not be
initialized correctly. Make sure that the WDTOVF signal* is not input logically to the RES pin. To reset the entire system
by means of the WDTOVF signal*, use the circuit shown in figure 13-9.
Note: * The WDTOVF pin function is not available in the F-ZTAT version, the H8S/2398, H8S/2394, H8S/2392 or
H8S/2390.
Rev.6.00 Oct.28.2004 page 463 of 1016
REJ09B0138-0600H