HD64F2357F20V Datasheet, PDF (135/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

6.1.2 Block Diagram
Figure 6-1 shows a block diagram of the bus controller.
CS0 to CS7
Area decoder
External bus control signals
BREQ
BACK
BREQO
ABWCR
ASTCR
BCRH
BCRL
Bus controller
Internal
address bus
Internal control
signals
Bus mode signal
WAIT
Wait controller
WCRH
WCRL
External DRAM
signals
DRAM controller
MCR
DRAMCR
RTCNT
RTCOR
Bus arbiter
CPU bus request signal
DTC bus request signal
DMAC bus request signal
CPU bus acknowledge signal
DTC bus acknowledge signal
DMAC bus acknowledge signal
Figure 6-1 Block Diagram of Bus Controller
Rev.6.00 Oct.28.2004 page 105 of 1016
REJ09B0138-0600H