HD64F2357F20V Datasheet, PDF (272/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

8.1.2 Block Diagram
Figure 8-1 shows a block diagram of the DTC.
The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1
kbyte), enabling 32-bit/1-state reading and writing of the DTC register information and hence helping to increase
processing speed.
Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1.
Interrupt controller DTC
Internal address bus
On-chip
RAM
Interrupt
request
CPU interrupt
request
Internal data bus
Legend:
MRA, MRB:
DTC mode registers A and B
CRA, CRB:
DTC transfer count registers A and B
SAR:
DTC source address register
DAR:
DTC destination address register
DTCERA to DTCERF: DTC enable registers A to F
DTVECR:
DTC vector register
Figure 8-1 Block Diagram of DTC
Rev.6.00 Oct.28.2004 page 242 of 1016
REJ09B0138-0600H