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| HD64F2357F20V Datasheet, PDF (173/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series | |||
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6.5.9 Byte Access Control
When DRAM with a Ã16 configuration is connected, the 2-CAS system can be used for the control signals required for
byte access.
When the CW2 bit is cleared to 0 in MCR, the 2-CAS system is selected. Figure 6-18 shows the control timing in the 2-
CAS system, and figure 6-19 shows an example 2-CAS system DRAM connection.
When only DRAM with a Ã8 configuration is connected, set the CW2 bit to 1 in MCR.
Tp
Tr
ø
A23 to A0
Row
Tc1
Tc2
Column
CSn, (RAS)
CAS
Byte control
LCAS
HWR, (WE)
Note: n = 2 to 5
Figure 6-18 2-CAS System Control Timing (Upper Byte Write Access)
H8S/2357 Group
(Address shift size set to 9 bits)
CS, (RAS)
CAS
LCAS
HWR, (WE)
A9
A8
A7
A6
A5
A4
A3
A2
A1
D15 to D0
2-CAS type 4-Mbit DRAM
256-kbyte x 16-bit configuration
9-bit column address
RAS
UCAS
LCAS
WE
A8
Low address
A7
input: A8 to A0
A6
Column address
input: A8 to A0
A5
A4
A3
A2
A1
A0
D15 to D0 OE
Figure 6-19 Example of 2-CAS System Connection
Rev.6.00 Oct.28.2004 page 143 of 1016
REJ09B0138-0600H
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