HD64F2357F20V Datasheet, PDF (143/1049 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series

6.2.4 Bus Control Register H (BCRH)
Bit
:
Initial value :
R/W
:
7
ICIS1
1
R/W
6
ICIS0
1
R/W
5
4
3
BRSTRM BRSTS1 BRSTS0
0
1
0
R/W
R/W
R/W
2
RMTS2
0
R/W
1
RMTS1
0
R/W
0
RMTS0
0
R/W
BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory
interface for areas 2 to 5 and area 0.
BCRH is initialized to H'D0 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset* or
in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted between bus cycles when
successive external read cycles are performed in different areas.
Bit 7
ICIS1
0
1
Description
Idle cycle not inserted in case of successive external read cycles in different areas
Idle cycle inserted in case of successive external read cycles in different areas
(Initial value)
Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted between bus cycles when
successive external read and external write cycles are performed .
Bit 6
ICIS0
0
1
Description
Idle cycle not inserted in case of successive external read and external write cycles
Idle cycle inserted in case of successive external read and external write cycles
(Initial value)
Bit 5—Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM interface.
Bit 5
BRSTRM
0
1
Description
Area 0 is basic bus interface
Area 0 is burst ROM interface
(Initial value)
Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface.
Bit 4
BRSTS1
0
1
Description
Burst cycle comprises 1 state
Burst cycle comprises 2 states
(Initial value)
Rev.6.00 Oct.28.2004 page 113 of 1016
REJ09B0138-0600H