MC68HC908AT32 Datasheet, PDF (99/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Functional Description
8.3.2.5 Special Programming Exceptions
The programming method described in 8.3.2.4 Programming the PLL does not account for two possible
exceptions. A value of 0 for N or L is meaningless when used in the equations given. To account for these
exceptions:
• A 0 value for N is interpreted the same as a value of 1.
• A 0 value for L disables the PLL and prevents its selection as the source for the base clock. See
8.3.3 Base Clock Selector Circuit.
8.3.3 Base Clock Selector Circuit
This circuit is used to select either the crystal clock, CGMXCLK, or the VCO clock, CGMVCLK, as the
source of the base clock, CGMOUT. The two input clocks go through a transition control circuit that waits
up to three CGMXCLK cycles and three CGMVCLK cycles to change from one clock source to the other.
During this time, CGMOUT is held in stasis. The output of the transition control circuit is then divided by
two to correct the duty cycle. Therefore, the bus clock frequency, which is one-half of the base clock
frequency, is one-fourth the frequency of the selected clock (CGMXCLK or CGMVCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives CGMOUT. The VCO clock
cannot be selected as the base clock source if the PLL is not turned on. The PLL cannot be turned off if
the VCO clock is selected. The PLL cannot be turned on or off simultaneously with the selection or
deselection of the VCO clock. The VCO clock also cannot be selected as the base clock source if the
factor L is programmed to a 0. This value would set up a condition inconsistent with the operation of the
PLL, so that the PLL would be disabled and the crystal clock would be forced as the source of the base
clock.
8.3.4 CGM External Connections
In its typical configuration, the CGM requires seven external components. Five of these are for the crystal
oscillator and two are for the PLL.
The crystal oscillator is normally connected in a Pierce oscillator configuration, as shown in Figure 8-3.
Figure 8-3 shows only the logical representation of the internal components and may not represent actual
circuitry. The oscillator configuration uses five components:
• Crystal, X₁
• Fixed capacitor, C₁
• Tuning capacitor, C₂ (can also be a fixed capacitor)
• Feedback resistor, R_B
• Series resistor, R_S (optional)
The series resistor (R_S) may not be required for all ranges of operation, especially with high-frequency
crystals. Refer to the crystal manufacturer’s data for more information.
Figure 8-3 also shows the external components for the PLL:
• Bypass capacitor, C_BYP
• Filter capacitor, C_F
Routing should be done with great care to minimize signal cross talk and noise. See 8.9 Acquisition/Lock
Time Specifications for routing information and more information on the filter capacitor’s value and its
effects on PLL performance.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
99