MC68HC908AT32 Datasheet, PDF (259/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Protocol Violation Protection
23.6.2 Interrupt Vectors
The MSCAN08 supports four interrupt vectors as shown in Table 23-1. The vector addresses are
dependent on the chip integration and are to be defined. The relative interrupt priority is also integration
dependent and is to be defined.
Table 23-1. MSCAN08 Interrupt Vector Addresses
Function
Wakeup
Error interrupts
Receive
Transmit
Source
WUPIF
RWRNIF
TWRNIF
RERRIF
TERRIF
BOFFIF
OVRIF
RXF
TXE0
TXE1
TXE2
Local
Mask
WUPIE
RWRNIE
TWRNIE
RERRIE
TERRIE
BOFFIE
OVRIE
RXFIE
TXEIE0
TXEIE1
TXEIE2
Global
Mask
I bit
23.7 Protocol Violation Protection
The MSCAN08 will protect the user from accidentally violating the CAN protocol through programming
errors. The protection logic implements these features:
• The receive and transmit error counters cannot be written or otherwise manipulated.
• All registers which control the configuration of the MSCAN08 can not be modified while the
MSCAN08 is on-line. The SFTRES bit in the MSCAN08 module control register (see 23.13.1
MSCAN08 Module Control Register) serves as a lock to protect the following registers:
– MSCAN08 module control register 1 (CMCR1)
– MSCAN08 bus timing register 0 and 1 (CBTR0 and CBTR1)
– MSCAN08 identifier acceptance control register (CIDAC)
– MSCAN08 identifier acceptance registers (CIDAR0–CIDAR3)
– MSCAN08 identifier mask registers (CIDMR0–CIDMR3)
• The TxCAN pin is forced to recessive if the CPU goes into stop mode.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
259