MC68HC908AT32 Datasheet, PDF (354/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Byte Data Link Controller-Digital (BDLC-D)
28.6.4 BDLC State Vector Register
This register is provided to substantially decrease the CPU overhead associated with servicing interrupts
while under operation of a multiplex protocol. It provides an index offset that is directly related to the
BDLC’s current state, which can be used with a user-supplied jump table to rapidly enter an interrupt
service routine. This eliminates the need for the user to maintain a duplicate state machine in software.
Address: $003E
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
I3
I2
I1
I0
0
0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 28-19. BDLC State Vector Register (BSVR)
I0, I1, I2, and I3 — Interrupt Source Bits
These bits indicate the source of the interrupt request that currently is pending. The encoding of these
bits are listed in Table 28-6.
Table 28-6. BDLC Interrupt Sources
BSVR I3 I2 I1 I0
Interrupt Source
$00 0 0 0 0 No interrupts pending
$04 0 0 0 1 Received EOF
$08 0 0 1 0 Received IFR byte (RXIFR)
$0C 0 0 1 1 BDLC Rx data register full (RDRF)
$10 0 1 0 0 BDLC Tx data register empty (TDRE)
$14 0 1 0 1 Loss of arbitration
$18 0 1 1 0 Cyclical redundancy check (CRC) error
$1C 0 1 1 1 Symbol invalid or out of range
$20 1 0 0 0 Wakeup
Priority
0 (lowest)
1
2
3
4
5
6
7
8 (highest)
Bits I0, I1, I2, and I3 are cleared by a read of the BSVR except when the BDLC data register needs
servicing (RDRF, RXIFR, or TDRE conditions). RXIFR and RDRF can be cleared only by a read of the
BSVR followed by a read of the BDLC data register (BDR). TDRE can either be cleared by a read of the
BSVR followed by a write to the BDLC BDR or by setting the TEOD bit in BCR2.
MC68HC908AT32 Data Sheet, Rev. 3.1
354
Freescale Semiconductor