MC68HC908AT32 Datasheet, PDF (268/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

MSCAN Controller
NOTE
To ensure data integrity, no registers of the transmit buffers shall be written
while the associated TXE flag is cleared.
To ensure data integrity, no registers of the receive buffer shall be read
while the RXF flag is cleared.
23.13 Programmer’s Model of Control Registers
The programmer’s model has been laid out for maximum simplicity and efficiency. Figure 23-13 gives an
overview on the control register block of the MSCAN08.
Addr.
Register
$0500
Module Control
Register 0 (CMCR0)
See page 270.
Read:
Write:
Reset:
$0501
Module Control
Register 1 (CMCR1)
See page 271.
Read:
Write:
Reset:
$0502
Bus Timing Register
0 (CBTR0)
See page 272.
Read:
Write:
Reset:
$0503
Bus Timing Register
1 (CBTR1)
See page 273.
Read:
Write:
Reset:
$0504
Receiver Flag ^Read:
Register (CRFLG) Write:
See page 274. _Reset:
$0505
Receiver Interrupt Read:
Enable Register _Write:
(CRIER)
See page 275. ^Reset:
$0506
Transmitter Flag ^Read:
Register (CTFLG) Write:
See page 276. _Reset:
$0507
Transmitter Control Read:
Register _Write:
(CTCR)
See page 277. ^Reset:
$0508
Ident. Acceptance Read:
Control Register _Write:
(CIDAC)
See page 277. ^Reset:
$0509
Reserved Read:
Bit 7
0
0
0
0
SJW1
0
SAMP
0
WUPIF
0
WUPIE
0
0
0
0
0
0
0
R
6
5
4
3
2
0
0
SYNCH
SLPAK
TLNKEN
0
0
0
0
0
0
0
0
0
LOOPB
0
0
0
0
0
SJW0
BRP5
BRP4
BRP3
BRP2
0
0
0
0
0
TSEG22 TSEG21 TSEG20 TSEG13 TSEG12
0
0
0
0
0
RWRNIF TWRNIF RERRIF TERRIF BOFFIF
0
0
0
0
0
RWRNIE TWRNIE RERRIE TERRIE BOFFIE
0
0
0
0
ABTAK2 ABTAK1 ABTAK0
0
0
TXE2
0
0
0
0
0
ABTRQ2 ABTRQ1 ABTRQ0
1
TXEIE2
0
0
0
0
0
0
0
0
IDAM1
IDAM0
0
0
0
0
0
R
R
R
R
R
1
Bit 0
SLPRQ SFTRES
0
1
WUPM CLKSRC
0
0
BRP1
BRP0
0
0
TSEG11 TSEG10
0
0
OVRIF
RXF
0
0
OVRIE
RXFIE
0
0
TXE1
TXE0
1
1
TXEIE1 TXEIE0
0
IDHIT1
0
IDHIT0
0
0
R
R
= Unimplemented
R
= Reserved
Figure 23-13. MSCAN08 Control Register Structure (Sheet 1 of 2)
MC68HC908AT32 Data Sheet, Rev. 3.1
268
Freescale Semiconductor