MC68HC908AT32 Datasheet, PDF (109/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 9
Configuration Register (CONFIG-1)
9.1 Introduction
This section describes the configuration register (CONFIG-1), which contains bits that configure these
options:
• Resets caused by the low-voltage inhibit (LVI) module
• Power to the LVI module
• LVI enabled during stop mode
• Stop mode recovery time (32 CGMXCLK cycles or 4096 CGMXCLK cycles)
• Computer operating properly module (COP)
• FLASH security feature⁽¹⁾
9.2 Functional Description
The configuration register is a write-once register. Out of reset, the configuration register will read the
default value. Once the register is written, further writes will have no effect until a reset occurs.
NOTE
If the LVI module and the LVI reset signal are enabled, a reset occurs when
V_DD falls to a voltage, LVI_TRIPF, and remains at or below that level for at
least nine consecutive CPU cycles. Once an LVI reset occurs, the MCU
remains in reset until V_DD rises to a voltage, LVI_TRIPR.
Address: $001F
Bit 7
Read:
LVISTOP
Write:
Reset: 0
R
6
5
R
LVIRST
1
1
= Reserved
4
LVIPWR
1
3
SSREC
0
2
COPRS
0
1
STOP
0
Figure 9-1. Configuration Register (CONFIG-1)
Bit 0
COPD
0
LVISTOP — LVI Stop Mode Enable Bit
LVISTOP enables the LVI module in stop mode. See Chapter 14 Low-Voltage Inhibit (LVI).
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
109