MC68HC908AT32 Datasheet, PDF (280/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

MSCAN Controller
23.13.13 MSCAN08 Identifier Mask Registers
The identifier mask registers specify which of the corresponding bits in the identifier acceptance register
are relevant for acceptance filtering.
Register Name and Address: CIDMR0 — $0514
Bit 7
6
5
4
3
2
1
Bit 0
Read:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Write:
Reset:
Unaffected by reset
Register Name and Address: CIDMR1 — $0515
Bit 7
6
5
4
3
2
1
Bit 0
Read:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Write:
Reset:
Unaffected by reset
Register Name and Address: CIDMR2 — $0516
Bit 7
6
5
4
3
2
1
Bit 0
Read:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Write:
Reset:
Unaffected by reset
Register Name and Address: CIDMR3 — $0517
Bit 7
6
5
4
3
2
1
Bit 0
Read:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Write:
Reset:
Unaffected by reset
Figure 23-26. Identifier Mask Registers
(CIDMR0–CIDMR3)
AM7–AM0 — Acceptance Mask Bits
If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier
acceptance register must be the same as its identifier bit before a match will be detected. The message
will be accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit
in the identifier acceptance register will not affect whether the message is accepted.
1 = Ignore corresponding acceptance code register bit.
0 = Match corresponding acceptance code register and identifier bits.
NOTE
The CIDMR0–CIDMR3 registers can be written only if the SFTRES bit in
the MSCAN08 module control register is set.
MC68HC908AT32 Data Sheet, Rev. 3.1
280
Freescale Semiconductor