MC68HC908AT32 Datasheet, PDF (327/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port F
27.7 Port F
Port F is a 4-bit special function port that shares four of its pins with the timer interface module (TIMA).
27.7.1 Port F Data Register
The port F data register contains a data latch for each of the six port F pins.
Address: $0009
Bit 7
6
5
4
3
2
Read: 0
0
0
0
PTF3
PTF2
Write: R
R
R
R
Reset:
Unaffected by reset
Alternate Function:
TACH5 TACH4
R
= Reserved
Figure 27-17. Port F Data Register (PTF)
1
PTF1
TACH3
Bit 0
PTF0
TACH2
PTF[3:0] — Port F Data Bits
These read/write bits are software programmable. Data direction of each port F pin is under the control
of the corresponding bit in data direction register F. Reset has no effect on PTF[3:0].
TACH[5:2] — Timer Channel I/O Bits
The PTF3/TACH5–PTF0/TACH2 pins are the TIMA input capture/output compare pins. The edge/level
select bits, ELSxB–ELSxA, determine whether the PTF3/TACH5–PTF0/TACH2 pins are timer channel
I/O pins or general-purpose I/O pins. See 25.8.4 TIMA Channel Status and Control Registers.
NOTE
Data direction register F (DDRF) does not affect the data direction of port F
pins that are being used by the TIMA. However, the DDRF bits always
determine whether reading port F returns the states of the latches or the
states of the pins. (See Table 27-6.)
27.7.2 Data Direction Register F
Data direction register F determines whether each port F pin is an input or an output. Writing a logic 1 to
a DDRF bit enables the output buffer for the corresponding port F pin; a logic 0 disables the output
buffer.
Address: $000D
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
DDRF3 DDRF2 DDRF1 DDRF0
Write: R
R
R
R
Reset: 0
0
0
0
0
0
0
0
R
= Reserved
Figure 27-18. Data Direction Register F (DDRF)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
327