MC68HC908AT32 Datasheet, PDF (296/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface (TIM-6)
NOTE
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0 percent
duty cycle generation and removes the ability of the channel to self-correct
in the event of software error or noise. Toggling on output compare can also
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
5. In the TIMA status control register (TASC), clear the TIMA stop bit, TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIMA channel
0 registers (TACH0H–TACH0L) initially control the buffered PWM output. TIMA status control register 0
(TASC0) controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A.
Setting MS2B links channels 2 and 3 and configures them for buffered PWM operation. The TIMA channel
2 registers (TACH2H–TACH2L) initially control the PWM output. TIMA status control register 2 (TASC2)
controls and monitors the PWM signal from the linked channels. MS2B takes priority over MS2A.
Setting MS4B links channels 4 and 5 and configures them for buffered PWM operation. The TIMA channel
4 registers (TACH4H–TACH4L) initially control the PWM output. TIMA status control register 4 (TASC4)
controls and monitors the PWM signal from the linked channels. MS4B takes priority over MS4A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIMA overflows. Subsequent output
compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and clearing the TOVx bit generates a 100
percent duty cycle output. (See 25.8.4 TIMA Channel Status and Control Registers.)
25.4 Interrupts
These TIMA sources can generate interrupt requests:
• TIM overflow flag (TOF) — The timer counter value changes on the falling edge of the internal bus
clock. The timer overflow flag (TOF) bit is set on the falling edge of the internal bus clock following
the timer rollover to $0000. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow
interrupt requests. TOF and TOIE are in the TIM status and control registers.
• TIMA channel flags (CH5F–CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x. Channel x TIMA CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE.
25.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby modes.
25.5.1 Wait Mode
The TIMA remains active after the execution of a WAIT instruction. In wait mode, the TIMA registers are
not accessible by the CPU. Any enabled CPU interrupt request from the TIMA can bring the MCU out of
wait mode.
If TIMA functions are not required during wait mode, reduce power consumption by stopping the TIMA
before executing the WAIT instruction.
MC68HC908AT32 Data Sheet, Rev. 3.1
296
Freescale Semiconductor