MC68HC908AT32 Datasheet, PDF (77/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 7
System Integration Module (SIM)
7.1 Introduction
This section describes the system integration module (SIM), which supports up to 24 external and/or
internal interrupts. Together with the central processor unit (CPU), the SIM controls all MCU activities. A
block diagram of the SIM is shown in Figure 7-2. Figure 7-1 is a summary of the SIM input/output (I/O)
registers. The SIM is a system state controller that coordinates CPU and exception timing. The SIM is
responsible for:
• Bus clock generation and control for CPU and peripherals:
– Stop/wait/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and computer operating properly (COP)
timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
• Modular architecture expandable to 128 interrupt sources
Addr.
Register Name
Bit 7
6
5
4
3
2
$FE00
SIM Break Status Register ^Read:
R
R
R
R
R
R
(SBSR) Write:
See page 89. _Reset:
Read: POR
PIN
COP
ILOP
ILAD
0
$FE01
SIM Reset Status Register (SRSR)
See page 90.
Write:
Reset: 1
X
0
0
0
0
$FE03
SIM Break Flag Control Register ^Read: _BCFE
R
R
R
R
R
(SBFCR) Write:
See page 91. _{Reset: 0}
Note: Writing a logic 0 clears SBSW
= Unimplemented
R = Reserved
Figure 7-1. SIM I/O Register Summary
1
Bit 0
SBSW
R
See note
0
LVI
0
X
0
R
R
0
X = Indeterminate
Table 7-1. I/O Register Address Summary
Register
Address
SBSR
$FE00
SRSR
$FE01
SBFCR
$FE03
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
77