MC68HC908AT32 Datasheet, PDF (127/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

COP Control Register
13.3.6 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears
the COP prescaler.
13.3.7 COPD
The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. See
Chapter 10 Configuration Register (CONFIG-2).
13.3.8 COPRS
The COPRS bit selects the state of the COP rate select timeout bit (COPRS) in the configuration register
($001F). Timeout periods can be 262,128 or 8,176 CGMXCLK cycles. See Chapter 10 Configuration
Register (CONFIG-2).
13.4 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to
$FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address: $FFFF
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Low byte of reset vector
Write:
Clear COP counter
Reset:
Unaffected by reset
Figure 13-2. COP Control Register (COPCTL)
13.5 Interrupts
The COP does not generate CPU interrupt requests or DMA service requests.
13.6 Monitor Mode
The COP is disabled in monitor mode when V_DD + V_Hi is present on the IRQ1/V_PP pin or on the RST pin.
13.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby modes.
13.7.1 Wait Mode
The COP remains active in wait mode. To prevent a COP reset during wait mode, periodically clear the
COP counter in a CPU interrupt routine or a DMA service routine.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
127