MC68HC908AT32 Datasheet, PDF (207/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Functional Description
• When changing to a larger output compare value, enable channel x TIMB overflow interrupts and
write the new value in the TIMB overflow interrupt routine. The TIMB overflow interrupt occurs at
the end of the current counter overflow period. Writing a larger value in an output compare interrupt
routine (at the end of the current pulse) could cause two output compares to occur in the same
counter overflow period.
19.3.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the
PTF5/TBCH1 pin. The TIMB channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIMB channel 0 status and control register (TBSC0) links channel 0 and channel
1. The output compare value in the TIMB channel 0 registers initially controls the output on the
PTE2/TACH0 pin. Writing to the TIMB channel 1 registers enables the TIMB channel 1 registers to
synchronously control the output after the TIMB overflows. At each subsequent overflow, the TIMB
channel registers (0 or 1) that control the output are the ones written to last. TSC0 controls and monitors
the buffered output compare function, and TIMB channel 1 status and control register (TBSC1) is unused.
While the MS0B bit is set, the channel 1 pin, PTF4/TBCH0, is available as a general-purpose I/O pin.
NOTE
Channels 2 and 3 and channels 4 and 5 can be linked to operate as
specified previously.
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. Writing to the active
channel registers is the same as generating unbuffered output compares.
19.3.4 Pulse-Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel, the TIMB can generate a PWM
signal. The value in the TIMB counter modulo registers determines the period of the PWM signal. The
channel pin toggles when the counter reaches the value in the TIMB counter modulo registers. The time
between overflows is the period of the PWM signal.
As Figure 19-3 shows, the output compare value in the TIMB channel registers determines the pulse width
of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIMB
to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIMB to
set the pin if the state of the PWM pulse is logic 0.
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PTBx/TCHx
PULSE
WIDTH
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 19-3. PWM Period and Pulse Width
OUTPUT
COMPARE
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
207