MC68HC908AT32 Datasheet, PDF (241/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

22.5 Port D
Port D is an 8-bit, general-purpose I/O port.
Port D
22.5.1 Port D Data Register
Port D is a 8-bit special function port that shares two of its pins with the timer interface modules.
Address: $0003
Bit 7
Read:
PTD7
Write:
Reset:
Alternate Functions:
6
PTD6
TACLK
5
PTD5
4
3
PTD4
PTD3
Unaffected by reset
TBCLK
2
PTD2
Figure 22-11. Port D Data Register (PTD)
1
PTD1
Bit 0
PTD0
PTD[7:0] — Port D Data Bits
PTD[7:0] are read/write, software programmable bits. Data direction of PTD[7:0] pins are under the
control of the corresponding bit in data direction register D.
NOTE
Data direction register D (DDRD) does not affect the data direction of port
D pins that are being used by the TIMA or TIMB. However, the DDRD bits
always determine whether reading port D returns the states of the latches
or logic 0.
TACLK/TBCLK — Timer Clock Input Bit
The PTD6/ATD14/TACLK pin is the external clock input for the TIMA. The PTD4/ATD12/TBCLK pin is
the external clock input for the TIMB. The prescaler select bits, PS[2:0], select PTD6/ATD14/TACLK
or PTD4/ATD12/TBCLK as the TIM clock input. (See 18.8.4 TIMA Channel Status and Control
Registers and 19.8.1 TIMB Status and Control Register.) When not selected as the TIM clock,
PTD6/ATD14/TACLK and PTD4/ATD12/TBCLK are available for general-purpose I/O. While
TACLK/TBCLK are selected corresponding DDRD bits have no effect.
22.5.2 Data Direction Register D
Data direction register D determines whether each port D pin is an input or an output. Writing a logic 1 to
a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output
buffer.
Address:
Read:
Write:
Reset:
$0007
Bit 7
DDRD7
0
6
DDRD6
0
5
DDRD5
0
4
DDRD4
0
3
DDRD3
0
2
DDRD2
0
1
DDRD1
0
Figure 22-12. Data Direction Register D (DDRD)
Bit 0
DDRD0
0
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
241