MC68HC908AT32 Datasheet, PDF (189/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Functional Description
determine that an input capture event has occurred by enabling input capture interrupts or by polling the
status flag bit.
The result obtained by an input capture will be two more than the value of the free-running counter on the
rising edge of the internal bus clock preceding the external transition. This delay is required for internal
synchronization.
The free-running counter contents are transferred to the TIMA channel status and control register
(TACHxH–TACHxL, see 18.8.5 TIMA Channel Registers) on each proper signal transition regardless of
whether the TIMA channel flag (CH0F–CH5F in TASC0–TASC5 registers) is set or clear. When the status
flag is set, a CPU interrupt is generated if enabled. The value of the count latched or “captured” is the time
of the event. Because this value is stored in the input capture register two bus cycles after the actual event
occurs, user software can respond to this event at a later time and determine the actual time of the event.
However, this must be done prior to another input capture on the same pin; otherwise, the previous time
value will be lost.
By recording the times for successive edges on an incoming signal, software can determine the period
and/or pulse width of the signal. To measure a period, two successive edges of the same polarity are
captured. To measure a pulse width, two alternate polarity edges are captured. Software should track the
overflows at the 16-bit module counter to extend its range.
Another use for the input capture function is to establish a time reference. In this case, an input capture
function is used in conjunction with an output compare function. For example, to activate an output signal
a specified number of clock cycles after detecting an input event (edge), use the input capture function to
record the time at which the edge occurred. A number corresponding to the desired delay is added to this
captured value and stored to an output compare register (see 18.8.5 TIMA Channel Registers). Because
both input captures and output compares are referenced to the same 16-bit modulo counter, the delay
can be controlled to the resolution of the counter independent of software latencies.
Reset does not affect the contents of the input capture channel registers.
18.3.3 Output Compare
With the output compare function, the TIMA can generate a periodic pulse with a programmable polarity,
duration, and frequency. When the counter reaches the value in the registers of an output compare
channel, the TIMA can set, clear, or toggle the channel pin. Output compares can generate TIMA CPU
interrupt requests.
18.3.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare pulses as described in 18.3.3
Output Compare. The pulses are unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIMA channel registers.
An unsynchronized write to the TIMA channel registers to change an output compare value could cause
incorrect operation for up to two counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new value prevents any compare during
that counter overflow period. Also, using a TIMA overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIMA may pass the new value before it is
written.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
189