MC68HC908AT32 Datasheet, PDF (198/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface (TIMA-4)
18.8.4 TIMA Channel Status and Control Registers
Each of the TIMA channel status and control registers:
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input capture trigger
• Selects output toggling on TIMA overflow
• Selects 100 percent PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
Register Name and Address: TASC0 — $0026
Bit 7
6
5
4
Read: CH0F
Write: 0
CH0IE
MS0B
MS0A
Reset: 0
0
0
0
3
ELS0B
0
2
ELS0A
0
1
TOV0
0
Bit 0
CH0MAX
0
Register Name and Address: TASC1 — $0029
Bit 7
6
5
4
Read: CH1F
0
CH1IE
MS1A
Write: 0
R
Reset: 0
0
0
0
3
ELS1B
0
2
ELS1A
0
1
TOV1
0
Bit 0
CH1MAX
0
Register Name and Address: TASC2 — $002C
Bit 7
6
5
4
Read: CH2F
Write: 0
CH2IE
MS2B
MS2A
Reset: 0
0
0
0
3
ELS2B
0
2
ELS2A
0
1
TOV2
0
Bit 0
CH2MAX
0
Register Name and Address: TASC3 — $002F
Bit 7
6
5
4
3
2
1
Bit 0
Read: CH3F
0
CH3IE
MS3A ELS3B ELS3A TOV3 CH3MAX
Write: 0
R
Reset: 0
0
0
0
0
0
0
0
R
= Reserved
Figure 18-7. TIMA Channel Status
and Control Registers (TASC0–TASC3)
CHxF — Channel x Flag
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIMA counter registers matches the value in the TIMA channel x registers.
MC68HC908AT32 Data Sheet, Rev. 3.1
198
Freescale Semiconductor