MC68HC908AT32 Datasheet, PDF (320/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

MC68HC08AS20 Emulator Input/Output Ports
When bit DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When bit DDRBx is a
logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 27-2 summarizes the operation of the port B pins.
Table 27-2. Port B Pin Functions
DDRB
Bit
PTB
Bit
I/O Pin
Mode
Accesses to
DDRB
Read/Write
0
X
Input, Hi-Z DDRB[7:0]
1
X
Output
DDRB[7:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
Accesses to PTB
Read
Pin
PTB[7:0]
Write
PTB[7:0]⁽¹⁾
PTB[7:0]
27.4 Port C
Port C is a 5-bit, general-purpose, bidirectional I/O port.
27.4.1 Port C Data Register
The port C data register contains a data latch for each of the five port C pins.
Address: $0002
Bit 7
6
5
Read: 0
0
0
Write: R
R
R
Reset:
R
= Reserved
4
3
PTC4
PTC3
Unaffected by reset
2
PTC2
1
PTC1
Bit 0
PTC0
Alternate
Functions:
R
R
R
R
R
MCLK
R
R
Figure 27-8. Port C Data Register (PTC)
PTC[4:0] — Port C Data Bits
These read/write bits are software-programmable. Data direction of each port C pin is under the control
of the corresponding bit in data direction register C. Reset has no effect on port C data.
MCLK — T12 System Clock Bit
The system clock is driven out of PTC2 when enabled by MCLKEN bit in PTCDDR7.
MC68HC908AT32 Data Sheet, Rev. 3.1
320
Freescale Semiconductor