MC68HC908AT32 Datasheet, PDF (301/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

25.8.4 TIMA Channel Status and Control Registers
Each of the TIMA channel status and control registers:
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input capture trigger
• Selects output toggling on TIMA overflow
• Selects 100 percent PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
I/O Registers
Register Name and Address: TASC0 — $0026
Bit 7
6
5
4
Read: CH0F
Write: 0
CH0IE
MS0B
MS0A
Reset: 0
0
0
0
3
ELS0B
0
2
ELS0A
0
Register Name and Address: TASC1 — $0029
Bit 7
6
5
4
Read: CH1F
0
CH1IE
MS1A
Write: 0
R
Reset: 0
0
0
0
3
ELS1B
0
2
ELS1A
0
Register Name and Address: TASC2 — $002C
Bit 7
6
5
4
Read: CH2F
Write: 0
CH2IE
MS2B
MS2A
Reset: 0
0
0
0
3
ELS2B
0
2
ELS2A
0
Register Name and Address: TASC3 — $002F
Bit 7
6
5
4
Read: CH3F
0
CH3IE
MS3A
Write: 0
R
Reset: 0
0
0
0
3
ELS3B
0
2
ELS3A
0
Register Name and Address: TASC4 — $0032
Bit 7
6
5
4
Read: CH4F
Write: 0
CH4IE
MS4B
MS4A
Reset: 0
0
0
0
3
ELS4B
0
2
ELS4A
0
Register Name and Address: TASC5 — $0035
Bit 7
6
5
4
Read: CH5F
0
CH5IE
MS5A
Write: 0
R
Reset: 0
0
0
0
R
= Reserved
3
ELS5B
0
2
ELS5A
0
Figure 25-7. TIMA Channel Status
and Control Registers (TASC0–TASC5)
1
TOV0
0
1
TOV1
0
1
TOV2
0
1
TOV3
0
1
TOV4
0
1
TOV5
0
Bit 0
CH0MAX
0
Bit 0
CH1MAX
0
Bit 0
CH2MAX
0
Bit 0
CH3MAX
0
Bit 0
CH4MAX
0
Bit 0
CH5MAX
0
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
301