MC68HC908AT32 Datasheet, PDF (54/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

FLASH Memory
4.6 FLASH Program/Verify Operation
Programming of the FLASH memory is done on a page basis. A page consists of eight consecutive bytes
starting from address $XXX0 or $XXX8. The purpose of the verify mode is to ensure that data has been
programmed with sufficient margin for long-term data retention. During verify, the control gates of the
selected memory bits are held at a slightly negative voltage by an internal charge pump. Reading the data
is the same as for ordinary read mode except that a built-in counter stretches the data access for an
additional eight cycles to allow sensing of the lower cell current. A verify can only follow a program
operation. To program and verify the FLASH memory:
1. Set the PGM bit. This configures the memory for program operation and enables the latching of
address and data for programming.
2. Read from the block protect register.
3. Write data to the eight bytes of the page being programmed. This requires eight separate write
operations.
4. Set the HVEN bit.
5. Wait for time, t_PROG.
6. Clear the HVEN bit.
7. Wait for time, t_HVTV.
8. Set the VERF bit.
9. Wait for time, t_VTP.
10. Clear the PGM bit.
11. Wait for time, t_HVD.
12. Read back data in verify mode. This is done in eight separate read operations which are each
stretched by eight cycles.
13. Clear the VERF bit.
NOTE
While these operations must be performed in the order shown, other
unrelated operations may occur between the steps.
This program/verify sequence is repeated throughout the memory until all data is programmed. For
minimum overall programming time and least program disturb effect, the sequence should be part of an
intelligent operation which iterates per page (See 4.5 FLASH Erase Operation).
4.7 Block Protection
Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target
application, provision is made for protecting blocks of memory from unintentional erase or program
operations due to system malfunction. This protection is done by reserving a location in the memory for
block protect information and requiring that this location be read from to enable setting of the HVEN bit.
When the block protect register is read, its contents are latched by the FLASH control logic. If the address
range for an erase or program operation includes a protected block, the PGM or ERASE bit is cleared
which prevents the HVEN bit in the FLASH control register from being set so that no high voltage is
allowed in the array.
When the block protect register is erased (all 0s), the entire memory is accessible for program and erase.
When bits within the register are programmed, they lock blocks of memory address ranges as shown in
4.8 FLASH Block Protect Register. The block protect register itself can be erased or programmed only
MC68HC908AT32 Data Sheet, Rev. 3.1
54
Freescale Semiconductor