MC68HC908AT32 Datasheet, PDF (89/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

SIM Registers
CPUSTOP
IAB
STOP ADDR
STOP ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
instruction.
Figure 7-15. Stop Mode Entry Timing
CGMXCLK
STOP RECOVERY PERIOD
INT/BREAK
IAB
STOP +1
STOP + 2 STOP + 2
SP
SP – 1
SP – 2
SP – 3
Figure 7-16. Stop Mode Recovery from Interrupt or Break
7.7 SIM Registers
The SIM has three memory mapped registers.
7.7.1 SIM Break Status Register
The SIM break status register contains a flag to indicate that a break caused an exit from stop or wait
mode.
Address: $FE00
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SBSW
R
R
R
R
R
R
R
Write:
See Note
Reset:
0
R
= Reserved
NOTE: Writing a logic 0 clears SBSW.
Figure 7-17. SIM Break Status Register (SBSR)
SBSW — SIM Break Stop/Wait Bit
This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break
interrupt. Clear SBSW by writing a logic 0 to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt.
0 = Stop mode or wait mode was not exited by break interrupt.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
89