MC68HC908AT32 Datasheet, PDF (246/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

MC68HC08AZ32 Emulator Input/Output Ports
PTF[6:0] — Port F Data Bits
These read/write bits are software programmable. Data direction of each port F pin is under the control
of the corresponding bit in data direction register F. Reset has no effect on PTF[6:0].
TACH[3:2] — Timer A Channel I/O Bits
The PTF1/TACH3–PTF0/TACH2 pins are the TIM input capture/output compare pins. The edge/level
select bits, ELSxB:ELSxA, determine whether the PTF1/TACH3–PTF0/TACH2 pins are timer channel
I/O pins or general-purpose I/O pins. See 18.8.1 TIMA Status and Control Register.
TBCH[1:0] — Timer B Channel I/O Bits
The PTF5/TBCH1–PTF4/TBCH0 pins are the TIMB input capture/output compare pins. The edge/level
select bits, ELSxB:ELSxA, determine whether the PTF5/TBCH1–PTF4/TBCH0 pins are timer channel
I/O pins or general-purpose I/O pins. See 19.8.1 TIMB Status and Control Register.
NOTE
Data direction register F (DDRF) does not affect the data direction of port F
pins that are being used by the TIM. However, the DDRF bits always
determine whether reading port F returns the states of the latches or the
states of the pins. See Table 22-6.
22.7.2 Data Direction Register F
Data direction register F determines whether each port F pin is an input or an output. Writing a logic 1 to
a DDRF bit enables the output buffer for the corresponding port F pin; a logic 0 disables the output
buffer.
Address:
Read:
Write:
Reset:
$000D
Bit 7
6
5
4
3
2
1
0
DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1
R
0
0
0
0
0
0
0
R
= Reserved
Figure 22-18. Data Direction Register F (DDRF)
Bit 0
DDRF0
0
DDRF[6:0] — Data Direction Register F Bits
These read/write bits control port F data direction. Reset clears DDRF[6:0], configuring all port F pins
as inputs.
1 = Corresponding port F pin configured as output
0 = Corresponding port F pin configured as input
NOTE
Avoid glitches on port F pins by writing to the port F data register before
changing data direction register F bits from 0 to 1.
Figure 22-19 shows the port F I/O logic.
MC68HC908AT32 Data Sheet, Rev. 3.1
246
Freescale Semiconductor