MC68HC908AT32 Datasheet, PDF (79/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

SIM Bus Clock Control and Generation
7.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 7-3. This clock can
come from either an external oscillator or from the on-chip phase-locked loop (PLL). See Chapter 8 Clock
Generator Module (CGM).
7.2.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator output (CGMXCLK) divided by four
or the PLL output (CGMVCLK) divided by four. See Chapter 8 Clock Generator Module (CGM).
7.2.2 Clock Startup from POR or LVI Reset
When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the
CPU and peripherals are inactive and held in an inactive phase until after 4096 CGMXCLK cycles. The
RST pin is driven low by the SIM during this entire period. The bus clocks start upon completion of the
timeout.
OSC1
CLOCK
SELECT
÷2
CGMVCLK
CIRCUIT
PLL
BCS
PTC3
MONITOR MODE
USER MODE
CGMXCLK
A
CGMOUT
B _S*
*When S = 1,
CGMOUT = B
CGM
Figure 7-3. CGM Clock Signals
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
SIM
7.2.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows CGMXCLK to clock the SIM
counter. The CPU and peripheral clocks do not become active until after the stop delay timeout. This
timeout is selectable as 4096 or 32 CGMXCLK cycles. See 7.6.2 Stop Mode.
In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the
module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
79