MC68HC908AT32 Datasheet, PDF (357/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Low-Power Modes
an end-of-frame (EOF) has been detected prior to issuing the WAIT instruction by the CPU. Otherwise,
the BDLC will not correctly receive the byte that woke it up.
If this mode is entered while the BDLC is receiving a message, the first subsequent received edge will
cause the BDLC to wake up immediately, generate a CPU interrupt request, and wait for the BDLC
internal operating clocks to restart and stabilize before normal communications can resume. Therefore,
the BDLC is not guaranteed to receive that message correctly.
NOTE
It is important to ensure all transmissions are complete or aborted prior to
putting the BDLC into stop mode.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
357