MC68HC908AT32 Datasheet, PDF (192/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface (TIMA-4)
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
18.3.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the
PTE2/TACH0 pin. The TIMA channel registers of the linked pair alternately control the pulse width of the
output.
Setting the MS0B bit in TIMA channel 0 status and control register (TASC0) links channel 0 and
channel 1. The TIMA channel 0 registers initially control the pulse width on the PTE2/TACH0 pin. Writing
to the TIMA channel 1 registers enables the TIMA channel 1 registers to synchronously control the pulse
width at the beginning of the next PWM period. At each subsequent overflow, the TIMA channel registers
(0 or 1) that control the pulse width are the ones written to last. TASC0 controls and monitors the buffered
PWM function, and TIMA channel 1 status and control register (TASC1) is unused. While the MS0B bit is
set, the channel 1 pin, PTE3/TACH1, is available as a general-purpose I/O pin.
Channels 2 and 3 can be linked to form a buffered PWM channel whose output appears on the
PTF0/TACH2 pin. The TIMA channel registers of the linked pair alternately control the pulse width of the
output.
Setting the MS2B bit in TIMA channel 2 status and control register (TASC2) links channel 2 and channel
3. The TIMA channel 2 registers initially control the pulse width on the PTF0/TACH2 pin. Writing to the
TIMA channel 3 registers enables the TIMA channel 3 registers to synchronously control the pulse width
at the beginning of the next PWM period. At each subsequent overflow, the TIMA channel registers (2 or
3) that control the pulse width are the ones written to last. TASC2 controls and monitors the buffered PWM
function, and TIMA channel 3 status and control register (TASC3) is unused. While the MS2B bit is set,
the channel 3 pin, PTF1/TACH3, is available as a general-purpose I/O pin.
NOTE
In buffered PWM signal generation, do not write new pulse width values to
the currently active channel registers. Writing to the active channel
registers is the same as generating unbuffered PWM signals.
18.3.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered PWM signals, use this initialization
procedure:
1. In the TIMA status and control register (TASC):
a. Stop the TIMA counter by setting the TIMA stop bit, TSTOP.
b. Reset the TIMA counter by setting the TIMA reset bit, TRST.
2. In the TIMA counter modulo registers (TAMODH–TAMODL), write the value for the required PWM
period.
3. In the TIMA channel x registers (TACHxH–TACHxL), write the value for the required pulse width.
4. In TIMA channel x status and control register (TSCx):
a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare
or PWM signals) to the mode select bits, MSxB–MSxA. (See Table 18-2.)
b. Write 1 to the toggle-on-overflow bit, TOVx.
MC68HC908AT32 Data Sheet, Rev. 3.1
192
Freescale Semiconductor