MC68HC908AT32 Datasheet, PDF (318/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

MC68HC08AS20 Emulator Input/Output Ports
READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
DDRAx
WRITE PTA ($0000)
PTAx
PTAx
READ PTA ($0000)
Figure 27-4. Port A I/O Circuit
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a
logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 27-1 summarizes the operation of the port A pins.
Table 27-1. Port A Pin Functions
DDRA
Bit
PTA
Bit
I/O Pin Mode
Accesses to
DDRA
Read/Write
0
X
Input, Hi-Z
DDRA[7:0]
1
X
Output
DDRA[7:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
Accesses to PTA
Read
Pin
PTA[7:0]
Write
PTA[7:0]⁽¹⁾
PTA[7:0]
27.3 Port B
Port B is an 8-bit special-function port that shares all of its pins with the analog-to-digital converter.
27.3.1 Port B Data Register
The port B data register contains a data latch for each of the eight port B pins.
Address: $0001
Read:
Write:
Bit 7
PTB7
6
PTB6
5
PTB5
4
PTB4
3
PTB3
2
PTB2
Reset:
Alternate Functions: ATD7
ATD6
ATD5
Unaffected by reset
ATD4
ATD3
ATD2
Figure 27-5. Port B Data Register (PTB)
1
PTB1
ATD1
Bit 0
PTB0
ATD0
PTB[7:0] — Port B Data Bits
These read/write bits are software programmable. Data direction of each port B pin is under the control
of the corresponding bit in data direction register B. Reset has no effect on port B data.
MC68HC908AT32 Data Sheet, Rev. 3.1
318
Freescale Semiconductor