MC68HC908AT32 Datasheet, PDF (271/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Programmer’s Model of Control Registers
23.13.2 MSCAN08 Module Control Register 1
Address:
Read:
Write:
Reset:
$0501
Bit 7
6
5
4
3
2
1
0
0
0
0
0
LOOPB WUPM
0
0
0
0
0
0
0
= Unimplemented
Figure 23-15. Module Control Register 1 (CMCR1)
Bit 0
CLKSRC
0
LOOPB — Loopback Self-Test Mode Bit
When this bit is set, the MSCAN08 performs an internal loopback which can be used for self-test
operation and the bit stream output of the transmitter is fed back to the receiver. The RxCAN input pin
is ignored and the TxCAN output goes to the recessive state (1). Note that in this state, the MSCAN08
ignores the ACK bit to ensure proper reception of its own message and will treat messages being
received while in transmission as received messages from remote nodes.
1 = Activate loopback self-test mode
0 = Normal operation
WUPM — Wakeup Mode Flag
This flag defines whether the integrated low-pass filter is applied to protect the MSCAN08 from
spurious wakeups (see 23.8.4 Programmable Wakeup Function).
1 = MSCAN08 will wake up the CPU only in cases of a dominant pulse on the bus which has a
length of at least t_wup.
0 = MSCAN08 will wake up the CPU after any recessive to dominant edge on the CAN bus.
CLKSRC — Clock Source Flag
This flag defines which clock source the MSCAN08 module is driven from (see 23.10 Clock System).
1 = The MSCAN08 clock source is CGMOUT (see Figure 23-7).
0 = The MSCAN08 clock source is CGMXCLK/2 (see Figure 23-7).
NOTE
The CMCR1 register can be written only if the SFTRES bit in the MSCAN08
module control register is set.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
271