MC68HC908AT32 Datasheet, PDF (136/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

External Interrupt (IRQ)
15.4 IRQ/V_PP Pin
A logic 0 on the IRQ1/V_PP pin can latch an interrupt request into the IRQ1 latch. A vector fetch, software
clear, or reset clears the IRQ1 latch.
If the MODE1 bit is set, the IRQ1/V_PP pin is both falling-edge sensitive and low-level sensitive. With
MODE1 set, both of these actions must occur to clear the IRQ1 latch:
• Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear
the latch. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACK1
bit in the interrupt status and control register (ISCR). The ACK1 bit is useful in applications that poll
the IRQ1/V_PP pin and require software to clear the IRQ1 latch. Writing to the ACK1 bit can also
prevent spurious interrupts due to noise. Setting ACK1 does not affect subsequent transitions on
the IRQ1/V_PP pin. A falling edge on IRQ1/V_PP that occurs after writing to the ACK1 bit latches
another interrupt request. If the IRQ1 mask bit, IMASK1, is clear, the CPU loads the program
counter with the vector address at locations $FFFA and $FFFB.
• Return of the IRQ1/V_PP pin to logic 1 — As long as the IRQ1/V_PP pin is at logic 0, the IRQ1 latch
remains set.
The vector fetch or software clear and the return of the IRQ1/V_PP pin to logic 1 can occur in any order.
The interrupt request remains pending as long as the IRQ1/V_PP pin is at logic 0. A reset will clear the latch
and the MODE1 control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE1 bit is clear, the IRQ1/V_PP pin is falling-edge sensitive only. With MODE1 clear, a vector
fetch or software clear immediately clears the IRQ1 latch.
The IRQF1 bit in the ISCR register can be used to check for pending interrupts. The IRQF1 bit is not
affected by the IMASK1 bit, which makes it useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ1/V_PP pin.
NOTE
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
15.5 IRQ Module during Break Interrupts
The system integration module (SIM) controls whether the IRQ1 interrupt latch can be cleared during the
break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear the
latches during the break state. See 7.7.3 SIM Break Flag Control Register.
To allow software to clear the IRQ1 latch during a break interrupt, write a logic 1 to the BCFE bit. If a latch
is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect the latch during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default
state), writing to the ACK1 bit in the IRQ status and control register during the break state has no effect
on the IRQ latch.
MC68HC908AT32 Data Sheet, Rev. 3.1
136
Freescale Semiconductor