MC68HC908AT32 Datasheet, PDF (323/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port D
TACLK — Timer Clock Input Bit
The PTD6/ATD14/TACLK pin is the external clock input for the TIMA. The prescaler select bits,
PS[2:0], select PTD6/ATD14/TACLK as the TIMA clock input. (See 25.8.1 TIMA Status and Control
Register.) When not selected as the TIMA clock, PTD6/ATD14/TACLK is available for general-purpose
I/O or as an ADC channel.
NOTE
Do not use ADC channel ATD14 when using the PTD6/ATD14/TACLK pin
as the clock input for the TIMA.
27.5.2 Data Direction Register D
Data direction register D determines whether each port D pin is an input or an output. Writing a logic 1 to
a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output
buffer.
Address:
Read:
Write:
Reset:
$0007
Bit 7
0
0
0
6
DDRD6
0
5
DDRD5
0
4
DDRD4
0
3
DDRD3
0
2
DDRD2
0
1
DDRD1
0
Figure 27-12. Data Direction Register D (DDRD)
Bit 0
DDRD0
0
DDRD[6:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears DDRD[6:0], configuring all port D pins
as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 27-13 shows the port D I/O logic.
READ DDRD ($0007)
WRITE DDRD ($0007)
RESET
WRITE PTD ($0003)
DDRDx
PTDx
PTDx
READ PTD ($0003)
Figure 27-13. Port D I/O Circuit
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
323