MC68HC908AT32 Datasheet, PDF (188/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface (TIMA-4)
Addr.
Register Name
Bit 7
6
5
4
3
2
$002B
Read:
Timer A Channel 1 Register
Bit 7
6
Low (TACH1L) Write:
See page 201. _Reset:
5
4
3
2
Indeterminate after reset
$002C
Timer A Channel 2 Status and Control ^Read:
Register (TASC2) Write:
See page 198. _Reset:
CH2F
0
0
CH2IE
0
MS2B
0
MS2A ELS2B ELS2A
0
0
0
$002D
Timer A Channel 2 Register ^Read: _{Bit 15}
14
High (TACH2H) Write:
See page 201.
Reset:
13
12
11
10
Indeterminate after reset
$002E
Read:
Timer A Channel 2 Register
Bit 7
6
Low (TACH2L) Write:
See page 201. _Reset:
5
4
3
2
Indeterminate after reset
Timer A Channel 3 Status and Control ^{Read: CH3F} _CH3IE
0
MS3A ELS3B ELS3A
$002F
Register (TASC3) Write: 0
R
See page 201. _{Reset: 0}
0
0
0
0
0
$0030
Timer A Channel 3 Register ^Read: _{Bit 15}
14
High (TACH3H) Write:
See page 201.
Reset:
13
12
11
10
Indeterminate after reset
$0031
Read:
Timer A Channel 3 Register
Bit 7
6
Low (TACH3L) Write:
See page 201. _Reset:
5
4
3
2
Indeterminate after reset
= Unimplemented
R = Reserved
Figure 18-2. TIM I/O Register Summary (Continued)
1
Bit 0
1
Bit 0
TOV2 CH2MAX
0
0
9
Bit 8
1
Bit 0
TOV3 CH3MAX
0
0
9
Bit 8
1
Bit 0
18.3.1 TIMA Counter Prescaler
The TIMA clock source can be one of the seven prescaler outputs or the TIMA clock pin,
PTD6/ATD14/TACLK. The prescaler generates seven clock rates from the internal bus clock. The
prescaler select bits, PS[2:0], in the TIMA status and control register select the TIMA clock source.
18.3.2 Input Capture
An input capture function has three basic parts: edge select logic, an input capture latch, and a 16-bit
counter. Two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value
of the free-running counter after the corresponding input capture edge detector senses a defined
transition. The polarity of the active edge is programmable. The level transition which triggers the counter
transfer is defined by the corresponding input edge bits (ELSxB and ELSxA in TASC0 through TASC3
control registers with x referring to the active channel number). When an active edge occurs on the pin of
an input capture channel, the TIMA latches the contents of the TIMA counter into the TIMA channel
registers, TACHxH–TACHxL. Input captures can generate TIMA CPU interrupt requests. Software can
MC68HC908AT32 Data Sheet, Rev. 3.1
188
Freescale Semiconductor