MC68HC908AT32 Datasheet, PDF (164/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Peripheral Interface Module (SPI)
The generic names of the SPI I/O registers are:
• SPI control register (SPCR)
• SPI status and control register (SPSCR)
• SPI data register (SPDR)
17.4 Functional Description
Figure 17-1 summarizes the SPI I/O registers and Figure 17-2 shows the structure of the SPI module.
Addr.
$0010
Register Name
SPI Control Register
(SPCR)
See page 178.
Read:
Write:
Reset:
Bit 7
SPRIE
0
6
5
4
3
2
1
Bit 0
R SPMSTR CPOL CPHA SPWOM SPE SPTIE
0
1
0
1
0
0
0
$0011
SPI Status and Control Register
(SPSCR)
See page 180.
Read:
Write:
Reset:
SPRF
R
0
ERRIE
0
OVRF
R
0
MODF
R
0
SPTE
R
1
MODFEN SPR1
0
0
SPR0
0
$0012
SPI Data Register ^{Read: R7}
R6
R5
R4
R3
R2
R1
R0
(SPDR) Write: T7
T6
T5
T4
T3
T2
T1
T0
See page 182. _Reset:
Unaffected by reset
R = Reserved
Figure 17-1. SPI I/O Register Summary
The SPI module allows full-duplex, synchronous, serial communication among the MCU and peripheral
devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be interrupt
driven. All SPI interrupts can be serviced by the CPU.
The following paragraphs describe the operation of the SPI module.
17.4.1 Master Mode
The SPI operates in master mode when the SPI master bit, SPMSTR (SPCR $0010), is set.
NOTE
Configure the SPI modules as master and slave before enabling them.
Enable the master SPI before enabling the slave SPI. Disable the slave SPI
before disabling the master SPI. See 17.13.1 SPI Control Register.
Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI
module by writing to the SPI data register. If the shift register is empty, the byte immediately transfers to
the shift register, setting the SPI transmitter empty bit, SPTE (SPSCR $0011). The byte begins shifting
out on the MOSI pin under the control of the serial clock. See Figure 17-3.
The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register.
(See 17.13.2 SPI Status and Control Register.) Through the SPSCK pin, the baud rate generator of the
master also controls the shift register of the slave peripheral.
MC68HC908AT32 Data Sheet, Rev. 3.1
164
Freescale Semiconductor