MC68HC908AT32 Datasheet, PDF (178/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Peripheral Interface Module (SPI)
The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and
reading the data register.
See Table 17-3.
Table 17-3. SPI Configuration
SPE SPMSTR MODFEN SPI Configuration
0
X
X
Not enabled
1
0
X
Slave
1
1
0
Master without MODF
1
1
1
Master with MODF
X = don’t care
State of SS Logic
General-purpose I/O;
SS ignored by SPI
Input-only to SPI
General-purpose I/O;
SS ignored by SPI
Input-only to SPI
17.12.5 V_SS (Clock Ground)
V_SS is the ground return for the serial clock pin, SPSCK, and the ground for the port output buffers. To
reduce the ground return path loop and minimize radio frequency (RF) emissions, connect the ground pin
of the slave to the V_SS pin.
17.13 I/O Registers
Three registers control and monitor SPI operation:
• SPI control register (SPCR, $0010)
• SPI status and control register (SPSCR, $0011)
• SPI data register (SPDR, $0012)
17.13.1 SPI Control Register
The SPI control register:
• Enables SPI module interrupt requests
• Selects CPU interrupt requests
• Configures the SPI module as master or slave
• Selects serial clock polarity and phase
• Configures the SPSCK, MOSI, and MISO pins as open-drain outputs
• Enables the SPI module
Address: $0010
Read:
Write:
Bit 7
SPRIE
6
5
4
3
2
1
R
SPMSTR CPOL CPHA SPWOM SPE
Reset: 0
0
1
0
1
0
0
R
= Reserved
Figure 17-12. SPI Control Register (SPCR)
Bit 0
SPTIE
0
MC68HC908AT32 Data Sheet, Rev. 3.1
178
Freescale Semiconductor