MC68HC908AT32 Datasheet, PDF (130/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Low-Voltage Inhibit (LVI)
V_DD
LOW V_DD
DETECTOR
LVIPWR
FROM CONFIG
CPU CLOCK
V_DD > LVI_TRIP = 0
V_DD < LVI_TRIP = 1
V_DD
DIGITAL FILTER
FROM CONFIG
LVIRST
ANLGTRIP
Stop Mode
Filter Bypass
LVIOUT
LVISTOP
FROM CONFIG
Figure 14-1. LVI Module Block Diagram
LVI RESET
Addr.
$FE0F
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
LVI Status Register ^{Read: LVIOUT}
0
0
0
0
0
0
0
(LVISR) Write:
See page 130. _{Reset: 0}
0
0
0
0
0
0
0
= Unimplemented
Figure 14-2. LVI I/O Register Summary
14.3.3 False Reset Protection
The V_DD pin level is digitally filtered to reduce false resets due to power supply noise. In order for the LVI
module to reset the MCU,V_DD must remain at or below the LVI_TRIPF level for nine or more consecutive
CPU cycles. V_DD must be above LVI_TRIPR for only one CPU cycle to bring the MCU out of reset.
14.4 LVI Status Register
The LVI status register flags V_DD voltages below the LVI_TRIPF level.
Address: $FE0F
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
0
0
0
0
0
0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-3. LVI Status Register (LVISR)
MC68HC908AT32 Data Sheet, Rev. 3.1
130
Freescale Semiconductor