MC68HC908AT32 Datasheet, PDF (270/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

MSCAN Controller
23.13.1 MSCAN08 Module Control Register
Address:
Read:
Write:
Reset:
$0500
Bit 7
6
0
0
5
4
3
2
1
0
SYNCH
SLPAK
TLNKEN
SLPRQ
0
0
0
0
0
0
0
= Unimplemented
Figure 23-14. Module Control Register 0 (CMCR0)
Bit 0
SFTRES
1
SYNCH — Synchronized Status Bit
This bit indicates whether the MSCAN08 is synchronized to the CAN bus and as such can participate
in the communication process.
1 = MSCAN08 synchronized to the CAN bus
0 = MSCAN08 not synchronized to the CAN bus
TLNKEN — Timer Enable Flag
This flag is used to establish a link between the MSCAN08 and the on-chip timer (see 23.9 Timer Link).
1 = The MSCAN08 timer signal output is connected to the timer.
0 = No connection
SLPAK — Sleep Mode Acknowledge Flag
This flag indicates whether the MSCAN08 is in module internal sleep mode. It shall be used as a
handshake for the sleep mode request (see 23.8.1 MSCAN08 Internal Sleep Mode).
1 = Sleep — MSCAN08 in internal sleep mode
0 = Wakeup — MSCAN08 will function normally
SLPRQ — Sleep Request, Go to Internal Sleep Mode Flag
This flag allows a request for the MSCAN08 to go into an internal power-saving mode (see 23.8.1
MSCAN08 Internal Sleep Mode).
1 = Sleep — The MSCAN08 will go into internal sleep mode if and as long as there is no activity on
the bus.
0 = Wakeup — The MSCAN08 will function normally. If SLPAK is cleared by the CPU, then the
MSCAN08 will wake up, but will not issue a wakeup interrupt.
SFTRES — Soft Reset Bit
When this bit is set by the CPU, the MSCAN08 immediately enters the soft reset state. Any ongoing
transmission or reception is aborted and synchronization to the bus is lost.
These registers will go into the same state as out of hard reset: CMCR0, CRFLG, CRIER, CTFLG, and
CTCR.
The registers CMCR1, CBTR0, CBTR1, CIDAC, CIDAR0–CIDAR3, and CIDMR0–CIDMR3 can only
be written by the CPU when the MSCAN08 is in soft reset state. The values of the error counters are
not affected by soft reset.
When this bit is cleared by the CPU, the MSCAN08 will try to synchronize to the CAN bus. If the
MSCAN08 is not in bus-off state, it will be synchronized after 11 recessive bits on the bus; if the
MSCAN08 is in bus-off state, it continues to wait for 128 occurrences of 11 recessive bits.
1 = MSCAN08 in soft reset state
0 = Normal operation
MC68HC908AT32 Data Sheet, Rev. 3.1
270
Freescale Semiconductor