MC68HC908AT32 Datasheet, PDF (347/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

BDLC CPU Interface
28.6.1 BDLC Analog and Round-Trip Delay
This register programs the BDLC to compensate for various delays of different external transceivers. The
default delay value is 16 µs. Timing adjustments from 9 µs to 24 µs in steps of 1 µs are available. The
BARD register can be written only once after each reset, after which they become read-only bits. The
register may be read at any time.
Address:
Read:
Write:
Reset:
$003B
Bit 7
ATE
1
6
5
0
RXPOL
1
0
= Unimplemented
4
3
2
1
Bit 0
0
BO3
BO2
BO1
BO0
0
0
1
1
1
Figure 28-15. BDLC Analog and Round-Trip Delay Register (BARD)
ATE — Analog Transceiver Enable Bit
The analog transceiver enable (ATE) bit is used to select either the on-board or an off-chip analog
transceiver.
1 = Select on-board analog transceiver
0 = Select off-chip analog transceiver
NOTE
This device does not contain an on-board transceiver. This bit should be
programmed to a logic 0 for proper operation.
RXPOL — Receive Pin Polarity Bit
The receive pin polarity (RXPOL) bit is used to select the polarity of an incoming signal on the receive
pin. Some external analog transceivers invert the receive signal from the J1850 bus before feeding it
back to the digital receive pin.
1 = Select normal/true polarity; true non-inverted signal from the J1850 bus; for example, the
external transceiver does not invert the receive signal
0 = Select inverted polarity, where an external transceiver inverts the receive signal from the J1850
bus
BO3–BO0 — BARD Offset Bits
Table 28-3 shows the expected transceiver delay with respect to BARD offset values.
Table 28-3. BDLC Transceiver Delay
BARD Offset Bits
BO[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
Corresponding Expected
Transceiver’s Delays (µs)
9
10
11
12
13
14
15
16
BARD Offset Bits
BO[3:0]
1000
1001
1010
1011
1100
1101
1110
1111
Corresponding Expected
Transceiver’s Delays (µs)
17
18
19
20
21
22
23
24
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
347